1. Field of the Invention
The present invention relates to a method of forming a polycrystalline silicon film on a substrate on which surface an oxide film is formed. The present invention relates to, in particular, a method of forming a polycrystalline silicon film capable of improving reliability for using an oxide film for a long time if the polycrystalline silicon film is used as a gate electrode.
2. Description of the Related Art
Normally, a polycrystalline silicon film formed by the CVD (or Chemical Vapor Deposition) method is used as a gate electrode in a semiconductor device. According to the normal CVD method, a polycrystalline silicon film can be formed by introducing silane gas (SiH.sub.4 gas) into a vertical or horizontal electric furnace in which several tens of substrates are inserted under a low pressure atmosphere. Conditions for film formation involve, for example, using a vertical furnace, keeping a substrate temperature 650.degree. C., internal pressure of 0.55 Torr and a silane gas flow rate of 1000 sccm. They will be referred to as "first film formation conditions" hereinafter.
FIG. 1 is graph showing the relationship between the interface roughness and the substrate position in a furnace in case of forming a polycrystalline silicon film under the first film formation conditions, wherein the vertical axis indicates the average roughness Rms of the interface between the polycrystalline silicon film and a gate oxide film which serves as a base for the polycrystalline silicon film and the horizontal axis indicates the substrate position in the furnace. The average interface roughness means an average value of the roughness in a single substrate. As shown in FIG. 1, if a polycrystalline silicon film is formed under the first film formation conditions, the average roughness Rms differs according to the substrate positions in the furnace. That is, as a substrate is put at the upper position in the furnace, the average roughness of the interface between the polycrystalline silicon film and the gate oxide film is higher.
In addition, a polycrystalline silicon film can be formed under conditions that the pressure of the interior of the furnace is 0.5 Torr and that silane gas flow rate is 1000 sccm with a substrate temperature in the furnace kept 600.degree. C. These conditions will be referred to as "the second film formation conditions" hereinafter. FIG. 2 is graph showing the relationship between the interface roughness and the substrate position in a furnace in case of forming a polycrystalline silicon film under the second film formation conditions, wherein the vertical axis indicates the average roughness Rms of the interface between the polycrystalline silicon film and a gate oxide film which serves as a base for the polycrystalline silicon film and the horizontal axis indicates the substrate position in the furnace. As shown in FIG. 2, if a polycrystalline silicon film is formed under the second film formation conditions, the average roughness of the interface between the polycrystalline silicon film and the gate oxide film is higher as a substrate is put at the lower position in the furnace.
However, the following problems occur if forming a polycrystalline silicon film under the conventional first or second film formation conditions and forming an MOS transistor having a gate electrode consisting of this polycrystalline silicon film.
FIGS. 3 and 4 are graphs each showing the relationship between the weibull of the upper substrate and the lower substrate in the furnace and the Qbd value, wherein the horizontal axis indicates the Qbd value. A Qbd value is an index for reliability for long-time use of an oxide film in MOS structure. If the Qbd value is higher, it is indicated that reliability for long-time use of an oxide film is better. It is noted that FIG. 3 concerns an MOS capacitor in case of using the polycrystalline silicon film obtained under the first film formation conditions as a gate electrode for the MOS capacitor and that FIG. 4 concerns an MOS capacitor in case of using the polycrystalline silicon film obtained under the second film formation conditions as a gate electrode for the MOS capacitor.
As shown in FIG. 3, if a polycrystalline silicon film is formed under the first film formation conditions, the Qbd value of the oxide film on a substrate put at a higher position in the furnace is lower than that of the oxide film on a substrate put at a lower position in the furnace. Also, as shown in FIG. 4, if a polycrystalline silicon film is formed under the second film formation conditions, the Qbd value of the oxide film on a substrate put at a lower position in the furnace is lower than that of the oxide film on a substrate put at a higher position in the furnace. Obviously, in the conventional polycrystalline silicon film formation method, the Qbd value of the oxide film varies according to the substrate position in the furnace and it is impossible to obtain a desired Qbd value.
A technique for improving the withstand voltage of a capacitive insulating film by setting the average roughness of the surface of the capacitive insulating film at 80.ANG. A or less in a semiconductor device having the capacitive insulating film between two polycrystalline silicon films, is disclosed (by, for example, Japanese Patent Application Laid-Open No. Hei-9-116095). The technique is intended to adjust the average roughness of the surface of the capacitive insulating film by controlling conditions for forming a polycrystalline silicon film which serves as a base of the capacitive insulating film.
However, a substrate serves as a base for a gate oxide film in MOS structure. It is, thus, impossible to apply the method described in Japanese Patent Application Laid-Open No. Hei-9-116095 to MOS structure.
Further, as a method for manufacturing a semiconductor device having a gate electrode of polycide structure, there is well known a method for forming a silicide layer on a polycrystalline silicon layer having an average surface roughness of 1 nm or less (Japanese Patent Application Laid-Open No. Hei-6-151353). According to the method, even if the line width of the gate electrode is made very small, it is possible to prevent the silicide layer from coagulating or peeling off and the sheet resistance of the electrode from increasing.
Nevertheless, the surface roughness of the gate oxide film or the roughness of the interface between the gate oxide film and the polycrystalline silicon film is not described in Japanese Patent Application Laid-Open No. Hei-6-151353. Thus, according to this method, it is impossible to improve the withstand voltage of the gate oxide film and reliability.